Sub-10 Microsecond AUTOSAR SecOC CMAC Acceleration

Hardware architectures for offloading Secure Onboard Communication (SecOC) message authentication from automotive CPUs.

The Challenge of Bus Cryptography Overhead

Software calculation of AES-CMAC on automotive microcontrollers can consume up to 25% of CPU cycles and introduce 100+ microseconds of latency per message, violating hard real-time deadlines. CanHSM implements a hardwired cryptographic pipeline that processes incoming frames directly from the CAN controller FIFO in under 8 microseconds.

Optimizing Truncated Authentication Tags

To preserve the 64-byte payload limit of CAN-FD, CanHSM supports dynamic MAC truncation conforming to AUTOSAR specifications, balancing collision probability against available network bandwidth.

AES-128-CMAC Silicon Pipeline: Calculating MACs across CAN-FD payloads in under 8 microseconds.
Zero Host CPU Utilization: Freeing engine management and ADAS cores from cryptographic processing overhead.
Truncated MAC Management: Efficiently appending 28-bit to 56-bit authentication tags to conserve bus bandwidth.
Asymmetric SecOC Fallback: Hardware ECDSA verification for infrequent, high-security broadcast announcements.

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