Sicurezza Hardware per Bus CAN e Accelerazione AUTOSAR SecOC

Impiego di coprocessori hardware per l'autenticazione in tempo reale dei bus veicolari, gestione anti-replay e cifratura a bassissima latenza del carico utile.

CanHSM In-Vehicle Network Security Architecture

Cryptographic Enclave: CAN Cryptographic Engine — AUTOSAR SecOC ASIC Core

Hardware Security Nodes & Co-Processors

  • AUTOSAR SecOC CMAC Pipeline
  • Freshness Value Manager (FVM)
  • CAN-FD / CAN-XL Transceiver Hub
  • Hardware Frame Filter & IDPS
  • Silicon Key Derivation Core

Architectural Layers & Silicon Defenses

  • Layer 1: Deterministic Physical CAN Interface (ISO 11898-1/2 CAN-FD / CiA 610-1 CAN-XL): Interfacing directly with high-speed differential transceivers, sniffing frames, and injecting cryptographic tags.
  • Layer 2: Real-Time MAC Generation & Verification (Hardware AES-128/192/256-CMAC Core): Computing 28-bit to 64-bit truncated MACs for authenticating payload data before transceiving.
  • Layer 3: Freshness Value Manager (FVM) Core (Synchronized Trip Counter & Reset Logic): Generating synchronized freshness values combining trip counters, reset counters, and message counts.
  • Layer 4: In-Vehicle Gateway & Domain Routing (Ethernet SOME/IP to CAN Translation): Translating authenticated CAN messages into automotive Ethernet packets without losing cryptographic context.

Cryptographic Telemetry & Compliance: < 8 µs (SecOC CMAC Processing Time) | 100% (Anti-Replay Freshness Enforce) | 20 Mbps (CAN-XL Wire-Speed Throughput) | Zero-CPU (Host Microcontroller Offload)

Eliminare le vulnerabilità di broadcast nelle reti veicolari interne

The Controller Area Network (CAN) bus is the central nervous system of modern vehicles, but its inherent broadcast design lacks source authentication or confidentiality. CanHSM introduces dedicated silicon coprocessors adjacent to the CAN transceiver, generating and verifying cryptographic Message Authentication Codes (MACs) at wire speed without impacting vehicle control deadlines.

Core Engineering Areas

Technical Publications

Related Cluster Architecture Specifications